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TTRN0110G 10 gbits/s clock synthesizer, 16:1 data multiplexer advance data sheet august 2000 features n fully-integrated 10 ghz clock synthesizer; 16:1 data multiplexer n supports standard oc-192/stm-64 data rate of 9.9532 ghz as well as fec rate of 10.6642 ghz n supported clocking modes include the following: supports forward directional clocking for parallel transfer of input data with 311 mhz or 622 mhz data clocks supports contradirectional clocking for parallel transfer of input data based on a 622 mhz output clock supports a clockless data transfer mode n allows a 155.52 mhz or 622.08 mhz reference clock with common pll loop filter components for both frequencies n additional 10 gbits/s cml serial data output for system loopback n supports 10 ghz clock output for clocked laser driver applications n loss of lock indication n single 3.3 v supply n lvds 622.08 mbits/s digital i/o n power dissipation as low as 1.2 w n available in a 198 bga package n jitter generation and jitter transfer compliant with the following: telcordia technologies * gr-1377 core itu-t g.825 itu-t g.958 n fully compatible with the optical interface forum specification oif99.102.5 * telcordia technologies is a registered trademark of bell com- munications research, inc. applications n sonet/sdh optical modules n sonet/sdh line origination equipment n sonet/sdh add/drop multiplexers n sonet/sdh cross connects n sonet/sdh test equipment n digital video transmission description the lucent technologies microelectronics group TTRN0110G device provides a 16:1 multiplexer, accepts 16 differential lvds data inputs and a 155.52 mhz or 622.08 mhz reference clock, and generates a cml 10 gbits/s clock and data output. both forward directional and contradirectional clocking schemes are supported for transferring data across the parallel interface. when contraclocking is used, the TTRN0110G provides one of four phases of a 622.08 mhz clock output back upstream to the data chip. the device also supports a clockless parallel data transfer mode. the TTRN0110G can be operated at either the standard oc-192/stm-64 data rate of 9.9532 ghz or at the fec rate of 10.6642 ghz.
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 2 lucent technologies inc. table of contents contents page features ...................................................................................................................... ............................................. 1 applications .................................................................................................................. ............................................ 1 description ................................................................................................................... ............................................. 1 pin information ............................................................................................................... .......................................... 4 functional overview ........................................................................................................... ....................................11 fec rate support .............................................................................................................. ....................................11 clock synthesizer operation ................................................................................................... ...............................11 clock synthesizer loop filter ................................................................................................. ............................. 11 clock synthesizer settling time ............................................................................................... ........................... 12 loss of lock indicator (lcklossn) ............................................................................................. ......................12 clock synthesizer generated jitter ............................................................................................ .........................12 clock synthesizer jitter transfer ............................................................................................. ............................13 multiplexer operation ......................................................................................................... ....................................14 10 ghz clock output enable (enck10g) .......................................................................................... .................14 loopback 10 ghz data output (lbdp/n, enlbdn) .................................................................................. .........14 reset (resetn) ................................................................................................................ ..................................14 clocking modes and timing adjustments ......................................................................................... .....................15 forward directional 622 clocking mode (clkmod[1:0] = 00, extcntr, piclkp/n, ovrflw) .....................15 forward directional 311 clocking mode (clkmod[1:0] = 10, extcntr, piclkp/n, ovrflw) .....................15 contradirectional clocking mode (clkmod[1:0] = 01, phadj[1:0], extcntr) ...............................................16 clockless transfer mode (clkmod[1:0]= 11, extcntr) ............................................................................ .....17 cml output structure (used on pins d10gp/n, ck10gp/n, lbdp/n) ................................................................. 18 absolute maximum ratings ...................................................................................................... ..............................19 handling precautions .......................................................................................................... ...................................19 operating conditions .......................................................................................................... ....................................19 electrical characteristics .................................................................................................... ....................................20 reference frequency (refclkp/n, reffreq) (standard sonet rate) ........................................................20 reference frequency (refclkp/n, reffreq) (fec rate) ........................................................................... .20 lvds, cmos, cml input and output pins ......................................................................................... ................21 timing characteristics ........................................................................................................ ....................................24 transmit timing ............................................................................................................... ....................................24 outline diagram ............................................................................................................... .......................................28 198-pin bga ................................................................................................................... .....................................28 ordering information .......................................................................................................... .....................................29
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 3 lucent technologies inc. description (continued) 0356(f)r.1 note: diagram is representative of device functionality and conceptual signal flow. internal implementation details may be diff erent than shown. figure 1. functional block diagram of TTRN0110G d0p d0n d1p d1n d15p d15n overflow extcntr clkmod[1:0] piclkp piclkn enck155n ck155p ck155n ck622p ck622n phadj[1:0] reffreq refclkp refclkn lcklossn acquisition indicator manual phase adjust divide by 4 decode timing generation input phase/ freq. detector charge pump divide by 16 register data buffer 16:1 multiplexer data retime to digital logic resetn enlbdn lbdp lbdn d10gp d10gn invdatn enck10g ck10gp ck10gn rrefcml rrefvco rreflvds testn tstckp fecn 01 lfp lfn vco test
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 4 lucent technologies inc. pin information 0642(f).a figure 2. pin diagram of 198-pin bga d e f g h j k l n p c b a m r 123456789101112131415 top veiw
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 5 lucent technologies inc. pin information (continued) table 1. pin assignments for 198-pin bga by pin number order note: refers to no ball. a ball has been removed for routing purposes. pin signal name pin signal name pin signal name pin signal name a1 gnd c1 gnd e1 gnd g1 gnd a2 gnd c2 gnd e2 gnd g2 gnd a3 gnd c3 gnd e3 gnd g3 gnd a4 gnd c4 v ccd e4 gnd g4 gnd a5 ck10gn c5 e5 g5 v ccd a6 gnd c6 gnd e6 gnd g6 gnd a7 ck10gp c7 e7 invdatn g7 gnd a8 gnd c8 e8 gnd g8 gnd a9 d10gn c9 e9 testn g9 gnd a10 gnd c10 gnd e10 gnd g10 gnd a11 d10gp c11 e11 gnd g11 gnd a12 gnd c12 gnd e12 gnd g12 lcklossn a13 gnd c13 e13 v cca g13 a14 gnd c14 e14 v cca g14 v ccd a15 gnd c15 tstckp e15 lfn g15 v cca b1 gnd d1 lbdp f1 lbdn h1 v ccd b2gnd d2 f2 h2gnd b3gnd d3 f3 h3gnd b4gnd d4 f4 h4 b5 d5gnd f5gnd h5gnd b6 gnd d6 f6 gnd h6 gnd b7 d7 v ccd f7 enlbdn h7 gnd b8 gnd d8 rrefcml f8 gnd h8 gnd b9 d9 v ccd f9 enck10g h9 gnd b10 gnd d10 f10 gnd h10 gnd b11 d11 gnd f11 gnd h11 gnd b12 gnd d12 f12 rreflvds h12 gnd b13 v ccd d13 gnd f13 v cca h13 gnd b14 gnd d14 gnd f14 rrefvco h14 resetn b15 gnd d15 gnd f15 lfp h15 clkmod[0]
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 6 lucent technologies inc. pin information (continued) table 1. pin assignments for 198-pin bga by pin number order (continued) note: refers to no ball. a ball has been removed for routing purposes. pin signal name pin signal name pin signal name pin signal name j1 d0p k13 enck155n m9 gnd p5 d8p j2 gnd k14 fecn m10 d15p p6 d9p j3 gnd k15 extcntr m11 gnd p7 d10p j4 gnd l1 d1p m12 gnd p8 d12n j5 v ccd l2 gnd m13 gnd p9 d13n j6 v ccd l3 gnd m14 refclkn p10 d14n j7 gnd l4 gnd m15 phadj[0] p11 ck155n j8 gnd l5 gnd n1 d2p p12 piclkn j9 gnd l6 v ccd n2 d3p p13 ck622n j10 gnd l7 gnd n3 d4n p14 gnd j11 gnd l8 v ccd n4 gnd p15 gnd j12 gnd l9 n5 d7n r1 gnd j13 v ccd l10 gnd n6 gnd r2 d5p j14ovrflw l11gnd n7d10n r3d5n j15 clkmod[1] l12 gnd n8 d12p r4 d6n k1 d0n l13 gnd n9 gnd r5 d8n k2 gnd l14 phadj[1] n10 d15n r6 d9n k3 gnd l15 reffreq n11 gnd r7 d11p k4 gnd m1 d1n n12 gnd r8 d11n k5 m2 gnd n13 gnd r9 d13p k6 gnd m3 d4p n14 refclkp r10 d14p k7 gnd m4 gnd n15 gnd r11 ck155p k8 gnd m5 d7p p1 d2n r12 piclkp k9 v ccd m6 gnd p2 d3n r13 ck622p k10 gnd m7 gnd p3 gnd r14 gnd k11 v ccd m8 p4 d6p r15 gnd k12
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 7 lucent technologies inc. pin information (continued) note: in table 2, when operating the TTRN0110G device at the oc-192/stm-64 rate, 10 gbits/s should be interpreted as 9.9532 gbits/s. when operating the TTRN0110G device at the rs fec oc-192/stm-64 rate, 10 gbits/s should be interpreted as 10.6642 gbits/s. table 2. pin descriptions10 gbits/s and related signals * differential pairs are indicated by p and n suffixes. for nondifferential pins, n at the end of the symbol name designates act ive-low. ? i = input, o = output. i u indicates an internal pull-up resistor on this pin. i d indicates an internal pull-down resistor on this pin. pin symbol * type ? level name/description a11 d10gp o cml data output (10 gbits/s nrz). 10 gbits/s differential data out- put. note that this data rate will scale by 15/14 when operating at the fec rate. a9 d10gn d1 lbdp o cml loopback data output. additional 10 gbits/s differential data output for system loopback. note that this data rate will scale by 15/14 when operating at the fec rate. f1 lbdn a7 ck10gp o cml clock output (10 ghz). 10 ghz differential clock output. note that this clock frequency will scale by 15/14 when operating at the fec rate. a5 ck10gn k14 fecn i u cmos fec rate (active-low). selects the normal oc-192/stm-64 rate of 9.9532 ghz or the fec rate of 10.6642 ghz. 0 = fec rate of 10.6642 ghz 1 or no connection = oc-192/stm-64 rate of 9.9532 ghz note that all input and output clock and data rates are scaled by 15/14 when operating at the fec rate. d8 rrefcml i analog resistor reference cml. cml current bias reference resistor. (see table 16, page 23 for values.) f9 enck10g i u cmos enable ck10gp/n clock output. 0 = ck10gp/n buffer powered off 1 or no connection = ck10gp/n buffer enabled f7 enlbdn i u cmos enable lbdp/n data output (active-low). 0 = lbdp/n buffer enabled 1 or no connection = lbdp/n buffer powered off e7 invdatn i u cmos invert d10g data output (active-low). 0 = invert 1 or no connection = noninvert c15 tstckp i cml test clock input. (buffer is powered down when testn = 1.) e9 testn i u cmos select test clock (active-low). 0 = select test clock 1 or no connection = select vco f14 rrefvco i analog resistor reference vco. vco bias reference resistor. connect a tbd k w resistor to v ccd .
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 8 lucent technologies inc. pin information (continued) note: in table 3, when operating the TTRN0110G device at the oc-192/stm-64 rate, 155 mbits/s should be interpreted as 155.52 mbits/s. when operating the TTRN0110G device at the rs fec oc-192/stm-64 rate, 155 mbits/s should be interpreted as 166.62 mbits/s. table 3. pin descriptions622.08 mbits/s and related signals * differential pairs are indicated by p and n suffixes. for nondifferential pins, n at the end of the symbol name designates act ive-low. ? i = input, o = output. i u indicates an internal pull-up resistor on this pin. i d indicates an internal pull-down resistor on this pin. pin symbol * type ? level name/description m10 d15p i lvds data input (622 mbits/s). 622 mbits/s differential data input. d15 is the most significant bit and is transmitted first on the d10gp/n output. note that the data rate will scale by 15/14 when operating at the fec rate. n10 d15n r10 d14p lvds p10 d14n r9 d13p lvds p9 d13n n8 d12p lvds p8 d12n r7 d11p lvds r8 d11n p7 d10p lvds n7 d10n p6 d9p lvds r6 d9n p5 d8p lvds r5 d8n m5 d7p lvds n5 d7n p4 d6p lvds r4 d6n r2 d5p lvds r3 d5n m3 d4p lvds n3 d4n n2 d3p lvds p2 d3n n1 d2p lvds p1 d2n l1 d1p lvds m1 d1n j1 d0p lvds k1 d0n
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 9 lucent technologies inc. pin information (continued) table 3. pin descriptions622.08 mbits/s and related signals (continued) * differential pairs are indicated by p and n suffixes. for nondifferential pins, n at the end of the symbol name designates act ive-low. ? i = input, o = output. i u indicates an internal pull-up resistor on this pin. i d indicates an internal pull-down resistor on this pin. table 4. pin descriptionsreset * differential pairs are indicated by p and n suffixes. for nondifferential pins, n at the end of the symbol name designates act ive-low. ? i = input, o = output. i u indicates an internal pull-up resistor on this pin. i d indicates an internal pull-down resistor on this pin. pin symbol * type ? level name/description r13 ck622p o lvds clock output (622 mhz). 622 mhz differential clock output. note that this clock frequency will scale by 15/14 when operating at the fec rate. p13 ck622n m15 l14 phadj[0] phadj[1] i t cmos phase adjust. adjusts phase of ck622 in 90 degree steps. r11 ck155p o lvds clock output (155 mhz). 155 mhz differential clock output. note that this clock frequency will scale by 15/14 when operating at the fec rate. p11 ck155n k13 enck155n i u cmos enable ck155p/n clock output (active-low). 0 = ck155p/n buffer enabled 1 or no connection = ck155p/n buffer powered off r12 piclkp i lvds parallel input clock (622 mhz). 622 mhz differential clock input used to register parallel data when using forward directional clocking mode. note that this clock frequency will scale by 15/14 when operating at the fec rate. p12 piclkn h15 j15 clkmod[0] clkmod[1] i u cmos clock mode select. selects clocking method for data transfer mode. 00 = forward directional clocking 01 = clockless transfer 11 or no connections = contraclocking g12 lcklossn o cmos loss of lock (active-low). 0 = pll out of lock k15 extcntr i d cmos external center. centers the pointers in the parallel data storage element. j14 ovrflw o cmos data storage overflow. indicates (active high) when an overflow has occurred in the parallel data storage element. n14 refclkp i lvds reference clock input (622.08 mhz or 155.52 mhz). note that this clock frequency must scale by 15/14 when operating the device at the fec rate. m14 refclkn l15 reffreq i u cmos reference clock frequency. selects frequency of refclkp/n. 0 = 155 mhz 1 or no connection = 622 mhz f15 lfp i analog loop filter pll. connect lfp and lfn to loop filter (see figure 3, page 11). e15 lfn f12 rreflvds i analog resistor reference lvds. lvds bias reference resistor. connect a tbd k w resistor to v ccd . pin symbol * type ? level name/description h14 resetn i u cmos reset (active-low). resets all synchronous logic. during a reset, the true data outputs are in the low state and the barred data outputs are in the high state. reset must be held active low for a minimum of 6.4 ns while the internal oscillator is active. 0 = reset 1 or no connection = normal operation
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 10 lucent technologies inc. pin information (continued) table 5. pin descriptionspower and ground note: v cca and v ccd have the same dc value, which is represented as v cc unless otherwise specified. however, high-frequency filtering is suggested between the individual supplies. * differential pairs are indicated by p and n suffixes. for nondifferential pins, n at the end of the symbol name designates act ive-low. ? i = input, o = output. i u indicates an internal pull-up resistor on this pin. i d indicates an internal pull-down resistor on this pin. pin symbol * type ? level name/description e13, e14, f13, g15 v cca ipower analog power supply (3.3 v). b13, c4, d7, d9, g5, g14, h1, j5, j6, j13, k9, k11, l6, l8 v ccd ipower digital power supply (3.3 v). a1a4, a6, a10, a12a15, b1b4, b6, b8, b10, b12, b14, b15, c1c3, c6, c10, c12, d5, d11, d13d15, e1e4, e6, e8, e10e12, f5, f6, f8, f10, f11, g1g4, g6g11, h2, h3, h5h13, j2j4, j7j12, k2k4, k6k8, k10, l2l5, l7, l10l13, m2, m4, m6, m7, m9, m11m13, n4, n6, n9, n11n13, n15, p3, p14, p15, r1, r14, r15 gnd i ground ground.
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 11 lucent technologies inc. functional overview the TTRN0110G performs the clock synthesis and 16:1 data multiplexing operations required to support 10 gbits/s* oc-192/stm-64 applications compliant with telcordia technologies and itu standards. parallel 622 mbits/s data is clocked into an input register. both forward directional and contradirectional clocking modes are supported as well as a clockless data transfer mode. the data is then multiplexed into a 10 gbits/s serial stream and output buffered for interfacing to a laser driver. a 10 ghz clock is synthesized from a reference clock and is used to retime the serial data. the 10 ghz clock is optionally available as an output. fec rate support the TTRN0110G will support both the normal oc-192/stm-64 rate of 9.9532 ghz and the forward error correction (fec) rate of 10.6642 ghz. the fecn pin selects the rate at which the part is operating. throughout this docu- ment, most specifications are given in terms of the normal operating rate only. all frequency-based specifications are to be multiplied by 15/14 when operating at the fec rate and all time-based specifications, with the exception of electrical signal rise and fall times, are to be multiplied by 14/15 when operating at the fec rate. for example, the reference clock would need to be applied at 166.628 mhz or 666.515 mhz and the parallel data interface would operate at 666.515 mhz when fecn = 0. clock synthesizer operation the clock synthesizer uses a pll to synthesize a 10 ghz clock from a reference frequency. a 622 mhz clock derived from the 10 ghz synthesized clock may be used to clock in the parallel data in contradirectional clocking applications. clock synthesizer loop filter a typical loop filter that provides adequate damping for less than 0.1 db of jitter peaking is shown in figure 3. con- nect the filter components to lfp and lfn. the component values can be varied to adjust the loop dynamic response (see table 6). table 6. clock synthesizer loop filter component values ? capacitor c1 should be either ceramic or nonpolar. 5-8061(f).c figure 3. clock synthesizer loop filter components * the oc-192/stm-64 data rate of 9.95328 gbits/s is typically approximated as 10 gbits/s in this document when referring to the application rate. similarly, the low-speed parallel interface data rate of 622.08 mbits/s is typically approximated as 622 mbits/s. the exa ct frequencies are used only when necessary for clarity. components values for 8 mhz loop bandwidth c1 ? tbd m f 10% c2, c3 tbd pf 20% r1 tbd w 5% c 3 c 2 c 1 r 1 lfn lfp
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 12 lucent technologies inc. clock synthesizer operation (continued) clock synthesizer settling time the clock synthesizer will acquire phase/frequency lock after a valid refclkp/n signal is applied. the actual time to acquire lock is a function of the loop bandwidth selected. the loop will acquire lock within 5 ms when using the external loop bandwidth components corresponding to a corner of less than 8 mhz. loss of lock indicator (lcklossn) the lcklossn pin indicates (active-low) when the clock synthesizer has exceeded phase-lock limits with the incoming refclkp/n phase. the lock detect function compares the phases of the input 155 mhz or 622 mhz clock at the refclkp/n pins with the internally generated 622 mhz output clock at the ck622p/n pin. when the phase difference in the two signals is close to zero as determined by a second internal phase detector and filter, the lock detect signal lcklossn is set to a logic high. when the phase difference between the two signals is changing at a rate exceeding the filter's cutoff frequency, the TTRN0110G is declared out of lock and lcklossn is set to a logic low. if a set of highly damped phase-locked loop parameters is chosen, lcklossn may exhibit more than one positive edge transition during the acquisition process before a steady logic-high state is achieved. upon a transition from the out-of-lock condition to the in-lock condition, the parallel data storage element pointers are centered. clock synthesizer generated jitter the clock synthesizers generated jitter performance meets the requirements shown in table 7. these specifica- tions apply to the jitter generated at the 10 ghz clock pins ck10gp/n when the jitter on the reference clock refclkp/n is within the specifications given in table 10 on page 20, and the loop filter components are chosen to provide a loop bandwidth of less than 8 mhz. table 7. clock synthesizer generated jitter specifications * this denotes the device specification for system sonet/sdh compliance when the loop filter in table 6 and figure 3 is used. parameter typical max (device) * unit generated jitter (p-p) sonet rate: measured with 50 khz to 80 mhz bandpass filter 1 ui = 1/9.95328 ghz tbd 0.09 uip-p generated jitter (p-p) fec rate: measured with ?? khz to ?? mhz bandpass filter 1 ui = (14/15)(9.95328 ghz) tbd 0.09 uip-p
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 13 lucent technologies inc. clock synthesizer operation (continued) clock synthesizer jitter transfer the clock synthesizers jitter transfer performance meets the requirement shown in figure 4 when the loop filter values shown in table 6 on page 11 are used. 5-8062(f).a figure 4. clock synthesizer jitter transfer 60 40 20 0 1k 10k 100k 1m 10m 50 30 10 100m frequency (hz) jitter out/jitter in (db) (8 mhz, 0.1 db)
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 14 lucent technologies inc. multiplexer operation the parallel 622 mbits/s data is clocked into an input buffer then clocked into a 16:1 multiplexer. the relationship between the parallel d[15:0]p/n input data and the serial output data d10gp/n is given in figure 5. the d15 bit is the most significant bit (msb) and is shifted out first in time in the serial output stream. 5-8063(f) figure 5. parallel input to serial output data relationship 10 ghz clock output enable (enck10g) the 10 ghz clock output ck10gp/n may be disabled by setting the enck10g pin to logic low. enck10g is an active-high cmos input with a pull-up resistor so the default condition will enable the ck10gp/n output and a ground or logic-low signal must be applied to disable the ck10gp/n output. when disabled, the ck10gp/n pins should be either left floating or be connected to a load which returns to v cc . the output must not be connected directly to ground when it is disabled. loopback 10 ghz data output (lbdp/n, enlbdn) an alternate 10 gbits/s cml data output is available on the lbdp/n pin. this pin is provided for use in system loopback testing and avoids the need for off-chip signal splitting of the data signal path. the alternate 10 gbits/s loopback data output may be enabled by setting the enlbdn pin to logic low. enlbdn enable is an active-low cmos input with a pull-up resistor so the default condition will disable the lbdp/n output, and a ground or logic- low signal must be applied to enable the loopback output. when disabled, the lbdp/n pin should be either left floating, or be connected to a load which returns to v cc . the output must not be connected directly to ground when it is disabled. reset (resetn) the resetn signal must be held active low for a minimum of 6.4 ns when the internal vco is active and running, in order for the internal logic to be completely reset. d15 d14 d1 d0 d15 time (d15 serially shifted out first) (d0 serially shifted out last) (msb) (lsb)
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 15 lucent technologies inc. clocking modes and timing adjustments the TTRN0110G supports four timing modes for the 622 mbits/s data input: forward directional 622, forward direc- tional 311, contradirectional, and clockless transfer, as selected by the clkmod[1:0] pins. forward directional 622 clocking mode (clkmod[1:0] = 00, extcntr, piclkp/n, ovrflw) in forward directional 622 clocking mode (clkmod[1:0] = 00), data is clocked into a 16-bit wide input register on the TTRN0110G device by the piclkp/n parallel input clock. the setup and hold times for the data relative to piclk are given in figure 8 on page 24 and table 18 on page 26. an internal data buffer is used to absorb timing drift between piclk and the internal clocks derived from the 10 ghz internal oscillator. a piclk phase drift of up to 1600 ps relative to the internal clocks can be absorbed by the buffer, as long as the bandwidth of this phase drift is less than 16 mhz. note that the read and write addresses for the data buffer must be initially reset in order for the buffer to absorb the full range of piclk phase drift. the read and write addresses for the data buffer are reset at the time the pll acquires lock and the loss of lock indicator transitions from the out-of-lock condition to the in-lock condition. after lcklossn goes high the buffer will be centered and data integrity will be obtained within approximately 2 m s. the data buffer can also be recentered by applying extcntr (active high) for a minimum of 6.4 ns. after extcntr goes low the buffer will be centered and data integrity will be lost and subsequently restored within approximately 2 m s. if the timing drift exceeds 1600 ps, the data buffer will indicate overflow with a logic-high signal on the ovrflw pin for a minimum of 6.4 ns. after a time interval of 4.8 ns after ovrflw goes low, the buffer will be recentered and data integrity will be lost and subsequently restored within approximately 2 m s. during the 11.2 ns between the rising edge of ovrflw and the recentering of the buffer, data integrity may be lost if the timing drift exceeds 2000 ps. if the output clock ck622p/n is not used when in clkmod[1:0] = 00, it can be left unconnected to conserve power. forward directional 311 clocking mode (clkmod[1:0] = 10, extcntr, piclkp/n, ovrflw) in forward directional 311 clocking mode (clkmod[1:0] = 10), data is clocked into a 16-bit wide input register on the TTRN0110G device by the piclkp/n parallel input clock. in contrast to forward directional 622 mode, the piclk signal is at half the data rate (311 mhz instead of 622 mhz). the setup and hold times for the data relative to piclk are given in figure 9 on page 24 and table 18 on page 26. an internal data buffer is used to absorb timing drift between piclk and the internal clocks derived from the 10 ghz internal oscillator. a piclk phase drift of up to 1600 ps relative to the internal clocks can be absorbed by the buffer, as long as the bandwidth of this phase drift is less than 500 khz. note that the read and write addresses for the data buffer must be initially reset in order for the buffer to absorb the full range of piclk phase drift. the read and write addresses for the data buffer are reset at the time the pll acquires lock and the loss of lock indicator transitions from the out-of-lock condition to the in-lock condition. after lcklossn goes high, the buffer will be centered and data integrity will be obtained within approximately 2 m s. the data buffer can also be recentered by applying extcntr (active high) for a minimum of 6.4 ns. after extcntr goes low, the buffer will be centered and data integrity will be lost and subsequently restored within approximately 2 m s. if the timing drift exceeds 1600 ps, the data buffer will indicate overflow with a logic-high signal on the ovrflw pin for a minimum of 6.4 ns. after a time interval of 4.8 ns after ovrflw goes low, the buffer will be recentered and data integrity will be lost and subsequently restored within approximately 2 m s. during the 11.2 ns between the rising edge of ovrflw and the recentering of the buffer, data integrity may be lost if the timing drift exceeds 2000 ps. if the output clock ck622p/n is not used when in clkmod[1:0] = 10 it can be left unconnected to conserve power.
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 16 lucent technologies inc. clocking modes and timing adjustments (continued) contradirectional clocking mode (clkmod[1:0] = 01, phadj[1:0], extcntr) in the contradirectional clocking mode (clkmod[1:0] = 01) the TTRN0110G device sends a 622 mhz clock with one of four user-selectable phases out to the upstream device for clocking the data toward the TTRN0110G. the user can program phadj[1:0] to adjust the phase of ck622p/n as a function of pwb layout and upstream device propagation delay in order to meet the setup and hold time of the 622 mbits/s data input to the TTRN0110G. phadj[1:0] changes the phase of the ck622p/n clock without changing the input data sampling time. phadj[1:0] setting information is given in table 8, and the phase relationship of ck622p/n for each phadj[1:0] setting is shown in figure 6. table 8. phadj settings for ck622 output clock (contraclocking mode) in this mode, the TTRN0110G input data still passes though the data buffer described in the forward directional clocking sections, however, there will no longer be any phase drift or overflow since the ck622p/n output serves as the master clock for the upstream device. the read and write addresses for the data buffer are initially reset at the time the pll acquires lock and the loss of lock indicator transitions from the out-of-lock condition to the in- lock condition. after lcklossn goes high the buffer will be recentered and data integrity will be obtained within approximately 2 m s. 5-8064(f).r2 figure 6. ck622 phase relation vs. phadj setting input pins phase phadj[1] phadj[0] 0 0 (see part a of figure 6.) 1 1 (see part b of figure 6.) 1 0 (see part c of figure 6.) 0 1 (see part d of figure 6.) a. (0 deg.) b. (C90 deg.) c. (C180 deg.) d. (C270 deg.) time
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 17 lucent technologies inc. clocking modes and timing adjustments (continued) clockless transfer mode (clkmod[1:0]= 11, extcntr) in clockless transfer mode (clkmod[1:0] = 11), data may be sent to the TTRN0110G device without providing piclkp/n. an internal delay-locked loop (dll) automatically produces a 622 mhz clock that is aligned to the parallel data based on the phase of the d0p/n data input. the skew of all data bits d[15:1]p/n relative to d0p/n must be less than 650 ps as shown in figure 11 on page 25. an internal data buffer is used to absorb timing drift between d0 and the internal clocks derived from the 10 ghz internal oscillator. a d0 phase drift of up to 1600 ps relative to the internal clocks can be absorbed by the buffer, as long as the bandwidth of this phase drift is less than 500 khz. note that the read and write addresses for the data buffer must be initially reset in order for the buffer to absorb the full range of d[15:0]p/n phase drift. the read and write addresses for the data buffer are reset at the time the pll acquires lock and the loss of lock indicator transitions from the out-of-lock condition to the in-lock condition. after lcklossn goes high the buffer will be centered and data integrity will be obtained within approximately 2 m s. the data buffer can also be recentered by applying extcntr (active high) for a minimum of 6.4 ns. after extcntr goes low the buffer will be centered and data integrity will be lost and subsequently restored within approximately 2 m s. if the timing drift exceeds 1600 ps, the data buffer will indicate overflow with a logic-high signal on the ovrflw pin for a minimum of 6.4 ns. after a time interval of 4.8 ns after ovrflw goes low the buffer will be recentered and data integrity will be lost and subsequently restored within approximately 2 m s. during the 11.2 ns between the rising edge of ovrflw and the recentering of the buffer, data integrity may be lost if the timing drift exceeds 2000 ps. if the output clock ck622p/n is not used when in clkmod[1:0] = 11, it can be left unconnected to conserve power. because the clockless data transfer mode uses the transitions on the d0 data bit as a phase reference for clocking the data, a constraint of a maximum number of consecutive zeroes of less than tbd data periods is placed on the d0 bit when operating in the clockless data transfer mode.
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 18 lucent technologies inc. cml output structure (used on pins d10gp/n, ck10gp/n, lbdp/n) the cml architecture is essentially a current-steering mechanism combined with an amplifier. this makes the out- put swing of the signal a function of the termination resistor and the output current. the on-chip, 50 w termination resistor provides a back termination and the output may be direct or ac-coupled to the load. for the direct coupled case, the 50 w load should be referenced to the positive 3.3 v supply, v cc . this will ensure dc levels that comply with the limits set in table 16 and table 17 on page 23. the value for rrefcml is also given in these tables. 0358(f) figure 7. typical cml output structure C + input signal 50 w 50 w rrefcml v cc iout x enable C + vref iref device-internal cml output buffer circuit 50 w 50 w c c external output termination iout iout 50 w 50 w v tt v tt note: shown for ac coupling; direct coupling may also be used.
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 19 lucent technologies inc. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used in the defined model. no industrywide standard has been adopted for the cdm. however, a standard hbm (resistance = 1500 w , capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes: operating conditions table 9. recommended operating conditions parameter min max unit power supply voltage (v cc ) v storage temperature C40 125 c pin voltage gnd C 0.5 v cc + 0.5 v device voltage TTRN0110G tbd parameter symbol min typ max unit power supply (dc voltage) 3.135 3.3 3.465 v ground v input voltage: low high v il v ih see table 13, table 14. see table 13, table 14. see table 13, table 14. v v temperature: ambient C40 85 c power dissipation: d10g active, ck10g disabled, lbd disabled p d 1.2 tbd w power dissipation: d10g active, ck10g active, lbd disabled p d 1.7 tbd w power dissipation: d10g active, ck10g active, lbd active p d 1.9 tbd w
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 20 lucent technologies inc. electrical characteristics reference frequency (refclkp/n, reffreq) (standard sonet rate) the device requires a 155.52 mhz or a 622.08 mhz differential lvds reference clock input. table 10 provides the characteristics of the refclkp/n input. table 10. reference frequency characteristics (standard sonet) * includes effects of power supply variation, temperature, electrical loading, and aging. the 20 ppm tolerance is required to meet sonet/sdh requirements. for non-sonet/sdh compliant systems, looser tolerances may apply. ? measured under one 3.3 v lvds load. includes frequency components up to 8 mhz. ? specified range is to be compatible with environmental specification of TTRN0110G. applications requiring a reduced temperature range may specify the reference frequency oscillator accordingly. reference frequency (refclkp/n, reffreq) (fec rate) the device requires a (15/14)155.52 mhz or a (15/14)622.08 mhz differential lvds reference clock input. table 11 provides the characteristics of the refclkp/n input. table 11. reference frequency characteristics (fec rate) * includes effects of power supply variation, temperature, electrical loading, and aging. the 20 ppm tolerance is required to meet sonet/sdh requirements. for non-sonet/sdh compliant systems, looser tolerances may apply. ? measured under one 3.3 v lvds load. includes frequency components up to 8 mhz. ? specified range is to be compatible with environmental specification of TTRN0110G. applications requiring a reduced temperature range may specify the reference frequency oscillator accordingly. parameter min typ max unit reference frequency (refclkp/n): when reffreq = 0 when reffreq = 1 155.52 622.08 mhz mhz reference frequency tolerance* C20 20 ppm duty cycle 40 60 % phase jitter ? tbd ps(rms) temperature ? C40 85 c supply voltage ? 3.00 3.60 v parameter min typ max unit reference frequency (refclkp/n): when reffreq = 0 when reffreq = 1 (15/14)155.52 (15/14)622.08 mhz mhz reference frequency tolerance* C20 20 ppm duty cycle 40 60 % phase jitter ? tbd ps(rms) temperature ? C40 85 c supply voltage ? 3.00 3.60 v
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 21 lucent technologies inc. electrical characteristics (continued) lvds, cmos, cml output pins notes: 1. for table 12 through table 19, v cc = 3.3 v 5%, tambient = C40 c to +85 c. 2. for more information on interpreting cml specifications, see the cml output structure (used on pins d10gp/n, ck10gp/n, lbdp/n) section on page 18. table 12. lvds output pin parametrics * as defined in the ieee ? standard 1596.3 -1996. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc. applicable pins symbol parameter conditions min typ max units ck622p/n, ck155p/n voh output voltage high, voa or vob rload = 100 w 1% 1475 mv vol output voltage low, voa or vob rload = 100 w 1% 925 mv |vod| output differential voltage rload = 100 w 1% 250 400 mv vos output offset voltage rload = 100 w 1% 1125 1275 mv ro differential output impedance vcm = 1.0 v and 1.4 v 80 100 280 w d ro ro mismatch between a & b vcm = 1.0 v and 1.4 v 10 % | d vod| change in |vod| between logic 0 and logic 1 rload = 100 w 1% 25 mv | d vos| change in |vos| between logic 0 and logic 1 rload = 100 w 1% 25 mv isa, isb output current driver shorted to gnd 24ma isab output current drivers shorted together 12ma |ixa|,|ixb| power-off output leakage tbd ma trised tfalld data vod: rise time, 20% to 80% fall time, 20% to 80% zload = 100 w 1% zload = 100 w 1% 200 200 450 450 ps ps trisec tfallc clock vod: rise time, 20% to 80% fall time, 20% to 80% zload = 100 w 1% zload = 100 w 1% 100 100 450 450 ps ps tskew1 differential skew* tbd ps tskew2 channel to channel* 200 ps
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 22 lucent technologies inc. electrical characteristics (continued) lvds, cmos, cml output pins (continued) table 13. lvds input pin parametrics * buffer will not produce output transitions when input is open-circuited. ? looser than icore/ieee spec of 10 w . table 14. cmos input pin characteristics table 15. cmos output pin characteristics applicable pins symbol parameter conditions min typ max units d[15:0]p/n, refclkp/n piclkp/n vcm input common mode voltage range avg(via,vib) 0 1200 2400 mv vdiff input peak differential voltage |via-vib| 100 800 mv vhyst threshold hysteresis* (+vid) C (Cvid) mv rin differential input impedance ? f = 250 mhz 80 100 120 w applicable pins symbol parameter conditions min max unit resetn, fecn, phadj[1:0], clkmod[1:0], reffreq, enck10g, enlbdn, enck155n, testn v ih input voltage high v cc C 1.0 v cc v v il input voltage low gnd 1.0 v i ih input current high leakage v in = v cc 10 m a i il input current low leakage v in = gnd C225 m a extcntr v ih input voltage high v cc C 1.0 v cc v v il input voltage low gnd 1.0 v i ih input current high leakage v in = v cc 225 m a i il input current low leakage v in = gnd C10 m a applicable pins symbol parameter conditions min max unit lcklossn ovrflw v oh output voltage high i oh = C4.0 ma v cc C 0.5 v cc v v ol output voltage low i ol = 4.0 ma gnd 0.5 v c l output load capacitance 15 pf
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 23 lucent technologies inc. electrical characteristics (continued) lvds, cmos, cml output pins (continued) table 16. cml output pin dc characteristics table 17. cml output pin dc characteristics (high amplitude data swing) applicable pins symbol parameter conditions min typ max unit d10gp/n, lbdp/n, ck10gp/n v ol output voltage low r l = 50 w, referenced to vcc rrefcml = tbd k w v cc C 1.2 v v oh output voltage high v cc + 0.3 v v amp voltage amplitude single-ended 400 500 600 mv applicable pins symbol parameter conditions min typ max unit d10gp/n, lbdp/n v ol output voltage low r l = 50 w, referenced to vcc rrefcml = tbd k w v cc C 1.6 v v oh output voltage high v cc + 0.3 v v amp voltage amplitude single-ended 600 700 800 mv ck10gp/n v ol output voltage low v cc C 1.2 v v oh output voltage high v cc + 0.3 v v amp voltage amplitude single-ended 400 500 600 mv
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 24 lucent technologies inc. timing characteristics note that all timing diagrams involving differential signals represent the positive signal as a solid line and the nega- tive signal as a dashed line. this is especially important when referencing the rising or falling edge of a differential signal. transmit timing figure 8 shows the required timing relationships between the input clock piclkp/n and the input data d[15:0]p/n in forward directional 622 clocking mode. 0359(f)r.1 figure 8. transmit timing waveforms (forward directional 622 clocking mode) figure 9 shows the timing relationships between the input clock piclkp/n and the input data d[15:0]p/n in for- ward directional 311 clocking mode. 0360(f)r.1 figure 9. transmit timing waveform (forward directional 311 clocking mode) piclkp/n d[15:0]p/n inputs inputs data 1 data 2 tsu thold tperiod piclkp/n d[15:0]p/n inputs inputs data 1 data 2 tsu thold tperiod (0.25)tperiod
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 25 lucent technologies inc. timing characteristics (continued) transmit timing (continued) figure 10 shows the timing relationships between the output clock ck622p/n and the input data d[15:0]p/n. this relationship is true for both the contraclocking mode and the clockless transfer mode. 0361(f)r.1 note: t su and t hold only apply in contraclocking mode when clkmod[1:0] = 01. figure 10. transmit timing waveform (contradirectional clocking mode) figure 11 shows the skew relationship between the d0p/n data remainder of the d[15:1]p/n data bus required to support clockless data transfer. 0362(f)r.1 figure 11. transmit timing waveform (clockless transfer mode) ck622p/n d[15:0]p/n inputs outputs data 1 data 2 tsu thold tperiod d0p/n d[15:1]p/n inputs input data 1 data 2 tskew tskew tperiod (0.5)tperiod
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 26 lucent technologies inc. timing characteristics (continued) transmit timing (continued) the output 622 mhz clock and data signals are specified in table 18. table 18. lvds input/output pin ac timing characteristics applicable pins symbol parameter conditions min typ max unit ck622p/n piclkp/n forward directional 622 duty cycle all signals differential 40 50 60 % t period clock period 1.6 ns piclkp/n forward directional 311 duty cycle all signals differential 45 50 55 % t period clock period 3.2 ns input timing d[15:0]p/n, ck622p/n piclkp/n t su setup from clock edge to d[15:0]p/n clkmod = 01, all signals differential tbd ns t hold hold from clock edge to d[15:0]p/n clkmod = 01, all signals differential tbd ns t rise , t fall rise, fall times: 20%80% all signals differential tbd tbd tbd ps t skew transition skew rise to fall C tbd 0 tbd ps
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 27 lucent technologies inc. timing characteristics (continued) transmit timing (continued) figure 12 shows the timing relationships between the output 10 ghz clock ck10gp/n and the output 10 gbits/s data d10gp/n. 0357(f)r.1 figure 12. transmit timing waveform with 10 ghz clock the output 10 ghz clock and data signals from figure 12 are characterized in table 19. table 19. cml output pin ac timing characteristics applicable pins symbol parameter conditions min typ max unit ck10gp/n duty cycle rrefcml = tbd k w r l = 50 w 40 50 60 % t period ck10gp/n clock period 100 ps d10gp/n, ck10gp/n t dd time delay from clock edge to data edge 30 50 70 ps ck10gp/n d10gp/n, lbdp/n t rise , t fall rise, fall times: 20%80% 15 25 35 ps t skew transition skew rise to fall C20 0 20 ps r loss output return loss: 10 ghz < 7 ghz 12 15 db db ck10gp/n d10gp/n output output data 1 data 2 tperiod tdd data 3
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 28 lucent technologies inc. outline diagram 198-pin bga note: dimensions are in millimeters. tolerance is 0.076 mm unless otherwise noted. 0627(f) a1 ball corner d e f g h j k l n p c b a 14 spaces @ 1.00 = 14.00 1.00 typ. a1 ball identifier zone seating plane solder ball 14 spaces @ 1.00 = 14.00 1.143 ref m 1234567891011121314 1.885 0.330 0.051 typ 0.3734 0.0013 15.00 0.080 15.00 0.080 0.330 0.051 typ dia. 15 r sqr sqr
advance data sheet TTRN0110G august 2000 10 gbits/s clock synthesizer, 16:1 data multiplexer 29 lucent technologies inc. ordering information device code package temperature comcode (ordering number) TTRN0110G 198-pin bga C40 c to +85 c 108698465
TTRN0110G advance data sheet 10 gbits/s clock synthesizer, 16:1 data multiplexer august 2000 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 2000 lucent technologies inc. all rights reserved september 2000 ds00-346hspl for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 3507670 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)

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